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spi: Refactor alignment processes for serial data output and chip sel… VUnit Tests #22: Commit 93b45b2 pushed by nselvara
August 23, 2025 09:49 1m 16s main
main
August 23, 2025 09:49 1m 16s
pll: Bugfix - Covert ps to ns VUnit Tests #21: Commit 1770df6 pushed by nselvara
August 19, 2025 21:36 1m 8s main
main
August 19, 2025 21:36 1m 8s
spi: Add configurable parameters for chip count and data width in ord… VUnit Tests #19: Commit 36f986b pushed by nselvara
August 18, 2025 18:22 3m 4s main
main
August 18, 2025 18:22 3m 4s
spi: Bugfix - Only one chip should be active VUnit Tests #18: Commit ba9c1ab pushed by nselvara
August 15, 2025 15:08 2m 4s v1.2.1
v1.2.1
August 15, 2025 15:08 2m 4s
ci/cd: Recreate Unisim/Xilinx library if VHDL is available VUnit Tests #17: Commit cddb204 pushed by nselvara
August 15, 2025 15:07 1m 55s v1.2.0
v1.2.0
August 15, 2025 15:07 1m 55s
VUnit Tests VUnit Tests #14: by nselvara
August 15, 2025 15:05 2m 10s v1.0.0
v1.0.0
August 15, 2025 15:05 2m 10s
spi: Bugfix - Only one chip should be active VUnit Tests #13: Commit ba9c1ab pushed by nselvara
August 15, 2025 14:33 1m 33s main
main
August 15, 2025 14:33 1m 33s
async_fifo: Fixed colours of texts and positioned the texts above the… VUnit Tests #12: Commit 9e9e996 pushed by nselvara
August 14, 2025 23:54 1m 50s main
main
August 14, 2025 23:54 1m 50s
ci/cd: Recreate Unisim/Xilinx library if VHDL is available VUnit Tests #11: Commit cddb204 pushed by nselvara
August 14, 2025 23:27 1m 9s main
main
August 14, 2025 23:27 1m 9s
feat: Add test report generation and update CI/CD test runner for xun… VUnit Tests #3: Commit 9ee8b1e pushed by nselvara
July 29, 2025 20:33 1m 24s main
main
July 29, 2025 20:33 1m 24s
Add VHDL-Utils as submodule in ip/vhdl_utils VUnit Tests #2: Commit 3675865 pushed by nselvara
July 29, 2025 20:32 1m 17s main
main
July 29, 2025 20:32 1m 17s