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Implementation of CVA6 on Xilinx ultrascal VCU118 #3044

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a1d8f76
implementation cvu118
1yacht Apr 29, 2025
d5306a7
update gitignore
1yacht Apr 29, 2025
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6 changes: 6 additions & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -52,3 +52,9 @@ Bender.lock
# Both following lines are needed to list contents of ISA manual build dir.
!/vendor/riscv/riscv-isa-manual/build/
!/vendor/riscv/riscv-isa-manual/build/*


#modif par moi
.venv
/corev_apu/fpga/ariane.*
/corev_apu/fpga/vivado_pid*
Comment on lines +55 to +60
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is this necessary ?

6 changes: 5 additions & 1 deletion Makefile
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Expand Up @@ -39,7 +39,7 @@ torture-logs :=
# custom elf bin to run with sim or sim-verilator
elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
# board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video
BOARD ?= genesys2
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We want to keep genesys2 as the default board.

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To use a different board, you can just add BOARD option:
make fpga BOARD=vcu118
This file update must be removed.

BOARD ?= vcu118
ALTERA_BOARD ?= DK-DEV-AGF014E3ES
ALTERA_FAMILY ?= "AGILEX"
ALTERA_PART ?= AGFB014R24B2E2V
Expand Down Expand Up @@ -86,6 +86,10 @@ else ifeq ($(BOARD), nexys_video)
XILINX_PART := xc7a200tsbg484-1
XILINX_BOARD := digilentinc.com:nexys_video:part0:1.1
CLK_PERIOD_NS := 40
else ifeq ($(BOARD), vcu118)
XILINX_PART := xcvu9p-flga2104-2L-e
XILINX_BOARD := xilinx.com:vcu118:part0:2.0
CLK_PERIOD_NS := 20
else
$(error Unknown board - please specify a supported FPGA board)
endif
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16 changes: 14 additions & 2 deletions corev_apu/fpga/Makefile
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@@ -1,5 +1,5 @@
VIVADO ?= vivado
VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
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We want to build the bitstream in batch by default. Does your build work in batch as well ?

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This can remain local update for your dev/tests.

VIVADOFLAGS ?= -nojournal -mode gui -source scripts/prologue.tcl

work-dir := work-fpga
bit := $(work-dir)/ariane_xilinx.bit
Expand All @@ -12,7 +12,19 @@ ips := xlnx_axi_clock_converter.xci \
xlnx_axi_quad_spi.xci \
xlnx_axi_gpio.xci \
xlnx_clk_gen.xci \
xlnx_mig_7_ddr3.xci
xlnx_mig_ddr4.xci \
xlnx_axi_dwidth_converter_512_64.xci

ips_standard := xlnx_axi_clock_converter.xci \
xlnx_axi_dwidth_converter.xci \
xlnx_axi_quad_spi.xci \
xlnx_axi_gpio.xci \
xlnx_clk_gen.xci

ips_ddr3 := xlnx_mig_7_ddr3.xci

ips_ddr4 := xlnx_mig_ddr4.xci \
xlnx_axi_dwidth_converter_512_64.xci
Comment on lines -15 to +27
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Are the new variable used ? It looks like you change the default behaviour genesys2, we do not want that.

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You can use the BOARD option to execute the section according to the desired configuration.
ifeq ($(BOARD), genesys2) #Existing code else ifeq ($(BOARD), vcu118) #Your updates endif
Indeed, BOARD option is passed through the make command in the Makefile at upper level.


ips := $(addprefix $(work-dir)/, $(ips))
ips-target := $(join $(addsuffix /ip/, $(addprefix $(ip-dir)/, $(basename $(ips)))), $(ips))
Expand Down
2,175 changes: 200 additions & 1,975 deletions corev_apu/fpga/constraints/vcu118.xdc
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10 changes: 9 additions & 1 deletion corev_apu/fpga/scripts/run.tcl
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Expand Up @@ -24,12 +24,16 @@ if {$::env(BOARD) eq "genesys2"} {
add_files -fileset constrs_1 -norecurse constraints/vc707.xdc
} elseif {$::env(BOARD) eq "nexys_video"} {
add_files -fileset constrs_1 -norecurse constraints/nexys_video.xdc
} elseif {$::env(BOARD) eq "vcu118"} {
add_files -fileset constrs_1 -norecurse constraints/vcu118.xdc
} else {
exit 1
}

read_ip { \
"xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \
"xilinx/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.srcs/sources_1/ip/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.xci" \
"xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \
Comment on lines -32 to +35
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Same comment, no change of default behaviour for genesys2.


"xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci" \
"xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci" \
"xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci" \
Expand Down Expand Up @@ -69,6 +73,10 @@ if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/nexys_video.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh}
set file "src/nexys_video.svh"
set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh"
} elseif {$::env(BOARD) eq "vcu118"} {
read_verilog -sv {src/vcu118.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh}
set file "src/vcu118.svh"
set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}
Expand Down
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