Implementation of CVA6 on Xilinx ultrascal VCU118 #3044
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❌ failed run, report available here. |
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*.str files should be deleted.
vcu118.xdc file was modified, was VCU118 already supported on CVA6 ?
I'm afraid there are a lot of change not compatible with already existing and supported board. Make sure your modification does not break others boards, notably in Makefiles and ariane_xilinx.sv
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| #modif par moi | ||
| .venv | ||
| /corev_apu/fpga/ariane.* | ||
| /corev_apu/fpga/vivado_pid* |
| @@ -39,7 +39,7 @@ torture-logs := | |||
| # custom elf bin to run with sim or sim-verilator | |||
| elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv | |||
| # board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video | |||
| BOARD ?= genesys2 | |||
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We want to keep genesys2 as the default board.
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To use a different board, you can just add BOARD option:
make fpga BOARD=vcu118
This file update must be removed.
| @@ -1,5 +1,5 @@ | |||
| VIVADO ?= vivado | |||
| VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl | |||
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We want to build the bitstream in batch by default. Does your build work in batch as well ?
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This can remain local update for your dev/tests.
| xlnx_mig_7_ddr3.xci | ||
| xlnx_mig_ddr4.xci \ | ||
| xlnx_axi_dwidth_converter_512_64.xci | ||
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| ips_standard := xlnx_axi_clock_converter.xci \ | ||
| xlnx_axi_dwidth_converter.xci \ | ||
| xlnx_axi_quad_spi.xci \ | ||
| xlnx_axi_gpio.xci \ | ||
| xlnx_clk_gen.xci | ||
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| ips_ddr3 := xlnx_mig_7_ddr3.xci | ||
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| ips_ddr4 := xlnx_mig_ddr4.xci \ | ||
| xlnx_axi_dwidth_converter_512_64.xci |
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Are the new variable used ? It looks like you change the default behaviour genesys2, we do not want that.
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You can use the BOARD option to execute the section according to the desired configuration.
ifeq ($(BOARD), genesys2) #Existing code else ifeq ($(BOARD), vcu118) #Your updates endif
Indeed, BOARD option is passed through the make command in the Makefile at upper level.
| "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ | ||
| "xilinx/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.srcs/sources_1/ip/xlnx_axi_dwidth_converter_512_64/xlnx_axi_dwidth_converter_512_64.xci" \ | ||
| "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \ |
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Same comment, no change of default behaviour for genesys2.
| @@ -1192,7 +1215,7 @@ xlnx_mig_7_ddr3 i_ddr ( | |||
| .app_sr_active ( ), // keep open | |||
| .app_ref_ack ( ), // keep open | |||
| .app_zq_ack ( ), // keep open | |||
| .ui_clk ( ddr_clock_out ), | |||
| .ui_clk ( clk_200MHz_ref ), // attention changement ici pour garder 200Mhz (pas nécessaire si pas utilisé ddr3) | |||
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Do not comment in french.
Hello,
I add the implementation of the board VCU118 for the CVA6. To test it you need the VCU118 lisence and you just need to make the command " make fpga" on the root directory. I used the digilent configuration and change the DDR config for the DDR4 of the VCU118.