The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style
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Jun 3, 2025 - Verilog
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design-compiler
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An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.
asic rtl verilog synthesis hdl vlsi digital-design demux icc2 floorplanning hardware-design clock-tree-synthesis rtl-to-gdsii design-compiler
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Updated
Jun 4, 2025
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