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rtl-to-gdsii

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BinatM / Neural-Engine

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SPEAR – Single Neuron Hardware Accelerator Engine. A collaborative hardware project combining full custom ASIC design and FPGA-based validation. The CHIP team designed a perceptron accelerator from RTL to GDSII using Synopsys tools and TSMC 28nm. The FPGA team built a working test platform on DE10-Lite. Developed with mentorship and technical suppo

asic fpga neural-network hardware verification rtl chip perceptron vlsi gdsii physical-design rtl-to-gdsii
  • Updated Aug 1, 2025

ramiomer94 / VLSI-design-projects

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This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
  • Updated Jul 12, 2025
  • Verilog

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