This project implements a synchronous ROM in SystemVerilog, featuring an 8-bit data width and 128 addressable locations. It supports clocked operation with separate read and write enable controls, using parameterized addressing for scalability.
Synchronous RAM module in SystemVerilog — Implements an 8-bit wide, 128-location Random Access Memory with read and write enable controls, clocked operation, active high reset and parameterized addressing. Suitable for FPGA/ASIC design projects, memory initialization, and digital system simulations.
Add a description, image, and links to the memory-design-and-verification topic page so that developers can more easily learn about it.
To associate your repository with the memory-design-and-verification topic, visit your repo's landing page and select "manage topics."