"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
-
Updated
Aug 13, 2023 - Verilog
#
rtl-design-and-verification
Here are 10 public repositories matching this topic...
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification
-
Updated
Aug 13, 2025 - C
A go-to repository for exploring, learning, and mastering RTL design and verification.
-
Updated
Dec 18, 2024 - Verilog
RV32I 5-Stage Pipelined CPU
-
Updated
Jan 8, 2025 - Verilog
-
Updated
Aug 4, 2023 - SystemVerilog
RISC-V RV32IM Core
-
Updated
Aug 11, 2025 - C++
My interests and some collaborations
config iot embedded scala dsp embedded-systems chisel verilog systemverilog computer-architecture soc uvm risc-v filter-design github-config uvm-verification digital-systems-design rtl-design-and-verification
-
Updated
Jan 13, 2023
Synchronous RAM module in SystemVerilog — Implements an 8-bit wide, 128-location Random Access Memory with read and write enable controls, clocked operation, active high reset and parameterized addressing. Suitable for FPGA/ASIC design projects, memory initialization, and digital system simulations.
-
Updated
Aug 11, 2025 - SystemVerilog
This project implements a synchronous ROM in SystemVerilog, featuring an 8-bit data width and 128 addressable locations. It supports clocked operation with separate read and write enable controls, using parameterized addressing for scalability.
-
Updated
Aug 11, 2025 - SystemVerilog
Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.
verilog systemverilog digital-design asic-verification hardware-verification fpga-projects rtl-design-and-verification
-
Updated
Aug 15, 2025 - Jupyter Notebook
Improve this page
Add a description, image, and links to the rtl-design-and-verification topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the rtl-design-and-verification topic, visit your repo's landing page and select "manage topics."